Circuits¶
A circuit is a set of blocks wired pin to pin. It runs in steps: at each step its inputs take new values, and every block computes its output from its inputs, at once. Blocks of state (delays, bistables, counters, timers) remember values from one step to the next.
Blocks and pins¶
A block has input pins on its left and output pins on its right. A wire
goes from an output pin to an input pin; an output can feed many inputs, an
input takes exactly one wire. Every block has a name, unique in its level:
the first free of its kind (in1, and2, const1, …) until you rename it.
The blocks are listed in Blocks: sources and sinks (In, Out, constants), logic, comparisons, arithmetic, the Switch, the Unit delay, the properties (Assertion, Target, Assume), subsystems, and the library blocks of intrepyd (EDA and PLC: multiplexers, flip-flops, shift registers, edge detectors, bistables, counters, timers).
Types¶
Every wire carries a value of one type:
| Type | Values |
|---|---|
bool |
true and false |
int8, int16, int32, int64 |
signed machine integers, which wrap around on overflow |
uint8, uint16, uint32, uint64 |
unsigned machine integers |
int |
unbounded integers |
real |
rational numbers, exact |
float16, float32, float64 |
IEEE floating point numbers |
An In block and a Constant have the type you give them; a Unit
delay the type it holds. The other blocks take their type from their
inputs, as intrepyd infers it: a comparison gives a bool, a sum the type
of its operands. The checker refuses a wire whose type does
not fit: two operands of different types, a number into a logic gate.
Time: the Unit delay¶
A Unit delay (1/z) is the circuit's memory: its output is its init
input at the first step, then at each step the value its next input had
at the step before. A loop of wires must go through one: a loop with no
delay in it would ask a value to be computed from itself, and the checker
refuses it.
The library's blocks of state (bistables, counters, timers) are built on the same latches: their outputs at a step depend on their inputs at the steps before.
Subsystems¶
A subsystem is a part of the circuit as one block. Select blocks and press Ctrl+G (or Make a subsystem in their right-click menu): each wire that crossed the selection becomes one of its pins. Inside, its In and Out blocks are its pins: add one to add a pin, rename it to rename the pin. Double-click a subsystem to open it; the breadcrumb in the toolbar leads back. Subsystems nest; Ungroup puts the blocks back.
The checker, Simulate and Verify see the whole circuit: a problem inside a
subsystem marks it, and its line in the problems list leads inside. In a
trace or a test, a block inside a subsystem is named after it:
alarm_logic.rs1.
Editing¶
- Add a block by typing its name on the canvas, from the palette's search, or by dragging it from the palette.
- Move blocks by dragging them, or with the arrow keys; they snap to the grid. Auto-arrange (the ⋯ menu) lays them out by their connections.
- Copy, cut, paste and duplicate with Ctrl+C, Ctrl+X, Ctrl+V and Ctrl+D; the blocks go on the clipboard as JSON, so they can be pasted into another circuit. A pasted block keeps its name if it is free.
- Wires are routed for you, around the blocks. To route one by hand, select it and drag its segments; Auto-route, in its right-click menu, gives it back to the router.
- The right-click menu of a block, a wire or the canvas lists its actions with their shortcuts (Shift+F10 opens it for the selection).
- The view: the canvas is endless. Pan with the wheel, Space+drag or the middle button; zoom with Ctrl+wheel or the corner's − and +; Fit shows the whole circuit.
Commands and shortcuts lists them all.